The present invention relates to a memory device having memory cells for storing data, a sense amplifier, by which the content of the relevant memory cell can be determined on the basis of the magnitude and/or the direction of a current flow established through a memory cell during the read-out thereof.
Memory devices of this type have been known for many years in innumerable embodiments.
In the development of memory devices, as also in the case of other electrical circuits, great efforts are made in an attempt to keep the energy consumption as low as possible, or to reduce it further. In this context, considerable success has already been achieved particularly in recent years. However, the energy consumption of memory devices is still too high for certain applications.
One of these applications is memory devices for use in contactless smart cards.
As is known, contactless smart cards are connected to other devices exclusively in a wire-free manner. Even the energy required for their operation is transmitted in a wire-free manner; it is extracted from electromagnetic oscillations received by the smart card and is buffer-stored in a capacitor. However, the energy that can be buffer-stored in smart cards is extremely low in particular owing to the highly restricted storage possibilities. Accordingly, components contained in wire-free smart cards must be able to be operated with a minimum of energy. Conventional memory devices do not yet satisfy this requirement.
Published, European Patent Application EP 0 390 404 A shows a memory device having nonvolatile memory cells, and also a sense amplifier and the driving thereof. The sense amplifier contains a sense amplifier having feedback inverters. A current branch that is driven by the bit line connected to the memory cell is connected in parallel with an input-side transistor of the sense amplifier. The output of the sense amplifier is fed back to an NMOS transistor in order to decouple the bit line from the sense amplifier. The NMOS transistor is connected in series with a PMOS transistor and is located on the side of the memory cell.
U.S. Pat. No. 5,258,669 shows a memory cell and also a read-out circuit in which the bit line capacitance is precharged from a current path connected to the supply voltage.
It is accordingly an object of the invention to provide a memory device which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which operates as intended with a minimum of energy.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory device. The memory device contains a terminal for supplying a pole of a supply voltage, a memory cell for storing data in a memory transistor, and a sense amplifier for ascertaining a content of the memory cell on a basis of a magnitude and/or a direction of a current flow established through the memory cell during a read-out of the memory cell. The sense amplifier has an output and complementary transistors coupled in series with each other, and the output of the sense amplifier is fed back to the complementary transistors. A current mirror has a mirror transistor coupled in series with the memory transistor and a current branch connected in parallel with one of the complementary transistors of the sense amplifier. The mirror transistor has a remote terminal remote from the memory cell. A current switch-off device is provided for interrupting the current flow through the memory cell to be read while the memory cell content is ascertained. The current switch-off device has a transistor connected between the remote terminal of the mirror transistor and the terminal for supplying the pole of the supply voltage.
The invention has the positive effect that the time during which electric currents flow in the memory device and the sense amplifier can be reduced to a minimum.
The invention further has the positive effect that this considerably shortens the time required for reading from the memory cells; as a result, the memory device and/or a system containing it has to be activated for a shorter time than has previously been the case.
The energy consumption of the memory device decreases in both cases; such memory devices can be operated as intended with a minimum of energy.
In accordance with an added feature of the invention, the mirror transistor is a PMOS transistor, the current branch has a PMOS transistor, the complementary transistor of the sense amplifier which is connected in parallel with the current branch is a PMOS transistor, and the transistor contained in the current switch-off device is a PMOS transistor.
In accordance with another feature of the invention, the mirror transistor, the PMOS transistor contained in the current branch of the current mirror circuit, and the complementary transistor of the sense amplifier which is connected in parallel with the current branch are directly connected to the terminal for the pole of the supply voltage.
In accordance with an additional feature of the invention, the sense amplifier has an inverter with an input and a feedback output forming the output of the sense amplifier. The transistor contained in the current switch-off device has a control input connected to the input of the inverter.
In accordance with a further feature of the invention, the sense amplifier outputs a signal which signals the content of the memory cell to be read. The signal is held in a previous state after the current flow through the memory cell to be read has been prevented by the current switch-off device.
In accordance with a further added feature of the invention, the process of preventing the current flow through the memory cell to be read, which is performed by the current switch-off device, is ended with an ending of a read-out operation of the memory cell.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory device. The memory device contains a memory cell for storing data and sense amplifier for ascertaining a content of the memory cell on a basis of a magnitude and/or a direction of a current flow established through the memory cell during a read-out of the memory cell. The sense amplifier is coupled to the memory cell. A node is connected to the memory cell, the node being precharged before the memory cell is read, and a discharge device is connected to the node for partly discharging again the node.
In accordance with an added feature of the invention, a bit line is provided, and the node is part of the bit line assigned to the memory cell to be read.
In accordance with an additional feature of the invention, the memory cell has a memory transistor with a terminal connected to the node.
In accordance with a further feature of the invention, the discharge device discharges the node to a potential that is established there when a current that is to be detected by the sense amplifier flows through the memory cell.
In accordance with another feature of the invention, the node is discharged before a beginning of the read-out of the memory cell by the sense amplifier.
In accordance with a concomitant feature of the invention, the node is discharged with an adjustable current.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.